In wireless communications, multiple-input, multiple-output (MIMO) systems are used to increase the data rate. However, MIMO systems dissipate much more power than other wireless systems, as MIMO systems power multiple transmitters (TX) and receivers (RX) simultaneously. MIMO systems also add complexity, as electronic circuits in MIMO systems require additional components and control to handle the plurality of TX and RX chains.
Generally, a wireless device communicating through a MIMO system only uses one transmitter or receiver at a time, but will coordinate the transition between using different TX and RX components. A MIMO device may use various forms of clock synchronization to ensure that the multiple transmitters and receivers are coordinated with each other and work in tandem. Such synchronization between various TX and RX chains includes synchronization of I and Q component signals (the “IQ path”) that are used by RF devices when employing some modulation techniques, such as quadrature phase-shift keying (QPSK). When generating each IQ path, a clock signal is sent to a timing circuit, one for each transmitter and receiver, which is used to help generate separate I and Q signals based on the frequency of the clock signal. The I and Q signals can be mixed with data bits and used in the modulation scheme to transmit data between devices in a wireless system.
However, the timing circuits that enable the multiple IQ paths have trouble maintaining synchronization with each other. For example, many components in timing circuits, such as frequency dividers used in the IQ-generation path, are flip-flops or similar discrete electronic components that include internal memory elements. For example, a flip-flop divider generates an output signal based on both a received clock signal at the divider's internal memory state. As a result, two dividers will only achieve time synchronization if they receive the same clock signal simultaneously while at the same initial memory state. However, if any flip-flop divider in the array of timing circuits receives a glitched clock signal or has a different internal memory state, the IQ path generated by the divider will no longer be synchronized with the others and may result in timing problems due to scaling of technology (e.g., race conditions).
In view of the foregoing, it would be desirable to synchronize multiple transmitters and receivers on the same wireless device. In particular, it would be desirable to effectively generate synchronized IQ paths for each transmitter and receiver on the wireless device.